The present disclosure relates to a semiconductor unit and an electronic apparatus each including a protective circuit that is configured to protect an internal circuit from damage caused by electrostatic discharge (ESD).
A typical semiconductor unit includes a protective circuit to protect an internal circuit from damage caused by electrostatic discharge. For example, Japanese Unexamined Patent Application Publication Nos. 2006-121007 and 2004-14929 disclose protection circuits each including a trigger circuit in which a predetermined time constant is set, an inverter, and an N-type MOS (Metal Oxide Semiconductor) transistor. The trigger circuit in Japanese Unexamined Patent Application Publication No. 2006-121007 is configured by connecting a resistor device and a capacitor device in series to each other between a power supply terminal and a ground terminal, and the trigger circuit in Japanese Unexamined Patent Application Publication No. 2004-14929 is configured by connecting a P-type MOS transistor and a capacitor device in series to each other between a power supply terminal and a ground terminal. In each of these protection circuits, the trigger circuit generates a trigger signal by rounding a waveform of a voltage signal caused by static electricity applied to the power supply terminal. Then, the inverter inverts the trigger signal, and the N-type MOS transistor changes from an OFF state to an ON state, based on the inverted trigger signal. Thus, the protection circuit discharges static electricity applied to the power supply terminal to a ground through the N-type MOS transistor.
Moreover, various techniques for transistors having high tolerance to static electricity have been disclosed. For example, Japanese Unexamined Patent Application Publication No. H2-271673 discloses a transistor achieving an improvement in tolerance to static electricity by providing regions that are not silicided between a gate and a source and between the gate and a drain.